 StarMOS is the latest generation of discrete MOSFETs from Semelab.
This new process is based on a patented self-aligned interdigitated open cell structure,
offering improved switching performance, reduced RDS(ON) and lower costs than previous generations.
25% lower RDS(ON) reduces conduction losses
Reduction of the RDS(ON) has been achieved by increasing the channel packing density of the chip.
- Shallow junction depths allow more active area
in the same chip area.
- "Over active area bonding" has further increased the
packing density by using previously inactive chip area that was devoted to source and gate
bond pads.
Reduced switching losses
StarMOS has an open cell structure, employing metal deposited over the polysilicon gate layer. This dramatically reduces the internal series gate resistance resulting in better signal propagation across the chip. Multiple gate and source bond wires reduce the series inductance associated with these terminals. The source and gate "fingers" have been shortened and the top metal layout has been optimised. The result is reduced turn-on and turn-off times and lower switching losses.
Lower Costs
Process simplification has reduced manufacturing cycle times and lowered production costs. In addition, some of the chip sizes have been shrunk adding further to the cost reductions.
| Feature |
Result |
Benefit |
|
| Increased packing density |
Lower RDS(ON) |
- Lower conduction losses
- Lower temperature
|
|
| Shallower diffusions |
Lower capacitances and gate charge |
- Faster switching speeds
- Less switching losses
|
|
| Redesigned rings |
Added 1200V capability |
- Improved reliability
- Lower leakage
|
|
| Chip layout changes |
More uniform signal propagation |
|
|
| Modified diffusion process |
Reduced leakage current |
|
|
|
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